1. Field of the Invention
The present invention relates to communication transceiver clock and data recovery (CDR) circuits, and, in particular, to a CDR incorporating digitally controlled lock to reference circuitry.
2. Description of the Related Art
In many data communication applications, Serializer and De-serializer (SerDes) devices facilitate the transmission between two points of parallel data across a serial link. Data at one point is converted from parallel data to serial data and transmitted through a communications channel to the second point where it received and converted from serial data to parallel data.
At high data rates, frequency-dependent signal loss from the communications channel (e.g., the signal path between the two end points of a serial link) as well as signal dispersion and distortion can occur. As such, the communications channel, whether wired, optical, or wireless, acts as a filter and might be modeled in the frequency domain with a transfer function. Correction for frequency dependent losses of the communications channel, and other forms of signal degradation, often requires signal equalization at a receiver of the signal. Equalization through use of one or more equalizers compensates for the signal degradation to improve communication quality. Equalization may also be employed at the transmit side to pre-condition the signal. Equalization, a form of filtering, generally requires some estimate of the transfer function of the channel to set its filter parameters. However, in many cases, the specific frequency-dependent signal degradation characteristics of a communications channel are unknown, and often vary with time. In such cases, an equalizer with adaptive setting of parameters providing sufficient adjustable range might be employed to mitigate the signal degradation of the signal transmitted through the communications channel. An automatic adaptation process is often employed to adjust the equalizer's response. Equalization might be through a front end equalizer, a feedback equalizer, or some combination of both.
A clock and data recovery (CDR) circuit detects timing of the input data stream and uses such detected timing to set correct frequency and phase of a local clock from which the sampling clock for data sampling is derived. As employed herein, “placing” a sampler (latch) in a data stream requires setting a voltage threshold and clocking phase of the sampler to detect a predetermined point in a data eye. Clocking the data sampler with a clock signal with known frequency and phase derived with respect to the detected symbol timing of data allows for clock recovery of symbols within the data stream generating the data eye.
CDR circuits form a critical part of the receiver in a SerDes device. The objective of the CDR circuit is to track the phase of a sampling clock based on some criterion, such as minimized mean-squared-error (MMSE). To track the phase of a sampling clock based on a given criterion, the CDR circuit generates (timing) error samples with respect to the data sampling clock, and adaptively sets the local clock phase used to derive the data sampling clock so as to minimize the timing error with respect to the criterion between successive sampling events. The CDR circuit desirably operates so as to achieve very low target bit-error-ratio (BER) (usually, on the order of le-12 or le-15). The CDR circuits commonly employed might be broadly classified into two categories: baud-rate CDR circuits and bang-bang CDR circuits, with each class having associated advantages and disadvantages.
Known methods and devices use direct control of a receiver's VCO (RXVCO) in a digitally controlled CDR. In these methods, one or more D/A converters convert the digital control word(s) from the CDR to an analog control signal to apply to the control voltage input of the VCO. To improve receiver jitter tolerance and overcome the impact of process variation on the VCO, the resolution of the word applied to control the VCO must generally be increased. To minimize the area, power and cost of the CDR and D/A converter(s), the resolution of the control word (i.e., the number of bits contained in the word) applied to the VCO is minimized. However, with a low resolution control word, the VCO output frequency step size produces significant quantization noise. This significant quantization noise results in degraded CDR jitter tolerance to low frequency periodic jitter, especially in those applications where the incoming serial data rate is modulated by a spread spectrum clock. Increasing the resolution of the control word to improve receiver jitter tolerance increases circuit area, increases device power, and increases circuit costs.
FIG. 1 shows an exemplary clock and data recovery (CDR) circuit 100 of prior art systems including receiver VCO (RXVCO) 110. Serial data, after potentially going through linear equalization and decision feedback equalization (DFE), is applied to data slicers 102 which sample data once per unit interval (or, more frequently, typically oversampling data by at least a factor of 2) to provide samples to phase detector 104, as well as to data recovery circuitry (not shown in FIG. 1). Sampled data provided to phase detector 104 allows CDR 100 to determine sampling clock alignment within the data eye of the received serial data, and perform clock recovery from the incoming serial data. Phase detector 104 generates sampling clock up and down phase adjustments (UP and DN, respectively), thereby providing sampling clock with adjusted frequency and phase to data slicers 102.
RXVCO 110 utilizes two control loops, proportional and integral, which allow for more precise tracking of the incoming data rate as its frequency deviates from the nominal rate. RXVCO 110 might be implemented as one or more D/A converters with their outputs fed to the control voltage input(s) of an inductor-capacitor (LC) oscillator with varactor-type control of the frequency, or as a ring-based VCO with current or voltage controlling the delay of its delay stages.
A phase update request from phase detector 104 might optionally utilize majority vote block 106, where multiple phase update requests are converted to a single up, down, or no phase update. The resulting phase update from majority vote block 106 might also be processed by optional gear shifting block 112 and multiplier 108. This processing by optional gear shifting block 112 and multiplier 108 might have a higher multiplication coefficient in the initial phase of locking to a serial data stream, providing for wider bandwidth, in order to reduce time-to-lock of RXVCO 110. After start-up, over the course of time, the gain of gear shifting block 112 and multiplier 108 is reduced, narrowing the CDR loop bandwidth, and, thus, reducing self-jitter characteristic of a non-linear bang-bang phase detector based implementation of CDR 100. The final phase update request from the gear shifting multiplier is applied as a proportional control word to RXVCO 110.
The output frequency FVCO of RXVCO 110 is a function of integral control word DI with KVCOI gain and proportional control word DP with KVCOP gain. Proportional control has a character of pulse width modulation control. Each time proportional control is applied for a limited duration of time, the proportional control causes a temporary change in frequency FVCO of RXVCO 110. As a result, phase ΦVCO of RXVCO 110 changes by some amount up or down without permanent change to frequency FVCO of RXVCO 110. The frequency (FVCO) and phase (ΦVCO) are given by relations (1) and (2).FVCO=F0+DI*KVCOI+DP*KVCOP  (1)ΦVCO=∫FVCOdt,  (2)where F0 is the characteristic RXVCO frequency with both proportional and integral controls held at zero, DP is the proportional control, KVCOP is the proportional VCO gain, DI is the integral control, and KVCOI is the integral VCO gain.
Returning to FIG. 1, the output from phase detector 104 might optionally be decimated in decimator 114, and might also be processed by optional gear shifting block 112 and multiplier 109. After this optional processing, the output from phase detector 104 is applied to limiting integrator 116. Integral control, unlike proportional control, changes for an extended duration of time until limiting integrator 116 accumulates a different integer value. The integer value of limiting integrator 116 is the integral control word applied to RXVCO 110. Processing frequency might be reduced through use of decimated output of phase detector 104 that is provided by decimator 114. Again, as described previously, the integral control is modified at startup through action of gear shifting control and multiplier 109. The integer value of limiting integrator 116 is a coarse quantization of integral control of RXVCO 110, and the fractional value is optionally used due to RXVCO 110 implementation limitations.
When serial data is not present at the input of data slicers 102, (which is usually indicated by RX Loss Of Signal LOS detector, not shown in FIG. 1), the CDR loop is no longer closed since phase detector 104 does not provide UP and DN signals to keep the RXVCO frequency phase locked to input serial data. Under this condition, the frequency and phase of RXVCO 110 might drift far from the expected data rate, making it impossible to lock to serial data when it becomes available again. In order to avoid this situation, the frequency and phase of RXVCO 110 is desirably held in lock to a reference clock until serial data is available again. One method of the prior art uses a counter-based lock to reference, and an exemplary block diagram of the counter-based lock to reference is shown in FIG. 2.
As given above, the equation for RXVCO output frequency as a function of proportional and integral controls can be expressed as in relations (1) and (2). The output frequency FVCO of the RXVCO is a function of integral control word DI with KVCOI gain and proportional control word DP with KVCOP gain. Proportional control has a character of pulse width modulation, and integral control is simply level based. FIG. 2 shows a portion of the CDR of FIG. 1 incorporating a counter-based lock to reference mode of operation of the prior art.
As shown in FIG. 2, counter-based lock to reference 200 comprises frequency divider 201, counter1 202, counter2 203, FSM (finite state machine) 204, and MUX 205, which are employed in combination with RXVCO 110 and limiting integrator 116 when loss of serial data to the CDR input data slicers is detected. Whenever the serial input goes down (e.g. a control signal LOS is set high) a Lock to Reference (L2R) mode is invoked. MUX 205, based on the L2R mode indication, switches the integral control from limiting integrator 116 to the output of FSM 204.
In L2R mode, the output signal frequency of RXVCO 110 is divided down in frequency divider 201 to the rate rationally related to the Reference Clock rate. The output of frequency divider 201 is counted in counter1 202 for a duration of a predefined number of Reference Clock periods that is counted with counter2 203. The count in counter1 202 is compared, by FSM 204, to the expected count over time interval of counter2 203 when RXVCO frequency is at the Reference Clock related rate, and an UP or DN adjustment is generated by FSM 204 based on the comparison. The UP or DN adjustment is made to the Integral RXVCO Control. After the adjustment, the counting cycle is repeated until return of the serial input (e.g. a control signal loss LOS is set low). At the end of L2R mode, when serial input is again present and used for closing RXVCO loop control, the integral control word is loaded into limiting integrator 116 to serve as an initial integral control word.
Size of counter1 202 is designed large enough in order to maintain close alignment of RXVCO rate to the Reference Clock rate. For example, if counter1 202 counts to 1,000, this count corresponds to a resolution of 1,000 ppm. Since frequency adjustment of the output signal of RXVCO 110 may take several counting cycles, the duration of time that RXVCO 110 is forced to stay in L2R mode might be significant. A counter-based lock to reference frequency detector takes hundreds of microseconds to adjust RXVCO frequency to the reference clock rate, which is unacceptable for SAS, SATA, and other applications since lock to reference is invoked at every loss of signal or after partial power down. A CDR is desirably ready in a few microseconds to start receiving serial data error free.